Languguage OS 2/Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO/language/embedded/mcu360/quicc.faq

Text File | 1994-10-20 | 29.7 KB | 698 lines

Frequently Asked Questions about the 68360
Last Modified: 1/14/94

Introduction:

    In order to provide more technical information to our customers,
we have compiled a list that contains helpful hints  and often asked
questions about the QUICC.  We plan to update this list  regularly so
that we can get pertinent information out faster and more  efficiently.
We ask that you read over this list to become familiar  with the format
so that you may quickly find the answer your question. You are encouraged
to reference this list, the user's manual, and errata before contacting
your local field person with  your question.  Any new questions will be
placed both in the heirarcy and in section 19, "New Questions".  If you
have any questions about the information contained in this list, please
contact your local Motorola Field Representative.

This list is available at the following locations
The Motorola BBS    [phone]
anonymous FTP         bode.ee.ualberta.ca
            directory:  /pub/motorola/mcu360

Thank You.

Current Errata Revision
-----------------------
Device Errata for A.2 silicon        12/20/93
UM Errata                08/08/93

Categories:
1. CPU32+
2. SIM60
3. Memory Controller
4. IDMA Channels
5. SDMA Channels
6. Timers
7. Risc CP
8. SCCs
    a. Serial Interface
    b. UART Controller
    c. HDLC Controller
    d. HDLC Bus Controller
    e. Appletalk Controller
    f. BISYNC Controller
    g. Transparent Controller
    h. Ethernet Controller
9. SMCs
    a. UART Mode
    b. Transparent Mode
10. SPI
11. Parallel Ports
12. 040 Companion Mode/Slave Mode
13. Electrical Specs
14. Packaging Specs
15. Current Device Availability
    a. Parts/QUADS board availability
16. QUADS Board
    a. QUICCBug
    b. 360sw
    c. Documentation
17. Demo Code
18. Application Notes
19. New Questions/Information (Since 12/20/93)

------------------------------------------------------------------------

1.  CPU32+

Question: What is the best case interrupt latency for the QUICC?
Answer: The CPU32+ has a best case interrupt latency of approximately 39
clocks. Add 3 clocks for the SIM60 interrupt arbitration hardware.

------------------------------------------------------------------------
2. SIM60

Question:  My 68360 doesn't seem to want to enter slave mode.  Sometimes
it will enter slave mode but it does not function properly when it does.
Answer:  A special reset sequence is needed to put the chip into slave
mode.  See the Device Errata (A.2) for more details. This is fixed in
Revision B of the part.

Question: Does the DRAM controller continue to refresh DRAM while the
processor is stopped in Background Debug Mode?
Answer: Yes (assuming that the DRAM controller was programmed to
do DRAM refresh of course).

Question: Can I use a BDM connector if the QUICC is in slave mode
Answer: No.  Since there is no CPU to control with a BDM connector. (The
680x0 line does not support Background Debug Mode)

Question: Can a 302 be used as a slave to a QUICC
Answer: Yes, it would appear to the 302 that it was talking to a 25 MHz
020.  Be sure to follow the 302 device errata related to using an
Asynchronous Bus.

Question: I can't seem to read or write MBAR in Master Mode.
Answer: MBAR is actually in CPU space, not in user or supervisor space.
Thus you must follow the procedure on page 6-30 of the UM.

Question: What is the difference between RESETS and RESETH?
Answer: RESETS was implemented to allow for a reset to occur that would
still retain the current settings of the SIM60 registers,
thus retaining the chip select mapping and DRAM Refresh during a reset.
The reset values for both RESETS and RESETH are shown in the memory map
on pages 3-5 through 3-11.  When an "H" is shown after the reset value,
it means that the register is only reset by a hard reset.

Question: I am trying to use the Show Internal Cycles feature but I am
not seeing any internal cycles on my logic analyzer.
Answer: Make sure that the logic analyzer is triggering off of DS*
rather than AS*.  In Show Cycles Mode, AS* is not toggled.  In addition,
it is possible that state mode of the logic analyzer will not work
due to the timing of DS* and the Data and Address Busses.  If you are
having problems, try wave mode.

Question: If I assert RESETS* and RESETH* at the same time, will both be
set in the status register?
Answer: Both RESET pins are asynchronous, thus they may be recognized on
different clocks.  If they are recognized on the same clock, or if RESETH*
is recognized first, both the EXT bit and the SRSTP bit will be set.
If RESETS* is recognized first, the register will reflect only a hard reset.

Question: Is it possible to run the QUICC from a 10 MHz external
oscillator and clock the CPU at 25 MHz?
Answer: Yes.  The system should be brought up with the MODCK pins
set to 01.  Once the system is running, the 128 prescaler should be
enabled and the MF set to 320.  (This is all done in the PLLCR)

Question: Is DPRAM cleared on hard reset?
Answer: No.

------------------------------------------------------------------------
3. Memory Controller

Question: If the QUICC is being used along with a external master. When
this external master is accessing DRAM when does the QUICC determine the
end of cycle. Is it the negation of CAS*, the negation of DSACK*, or the
negation of AS*.
Answer: It depends on the SYNC bit. If SYNC=0 then DSACK* rises after
AS*,thus it is the negation of  AS*. If SYNC = 1 it is according to the
bus cycle. i.e. S5 (which is  determined according to DSACK* assertion
settings in the memory controller configuration registers).

Question:  If the BSTM and SYNC is set for async operation (both set to 0).
What will  the parity bits indicate on output from the QUICC.?
Answer: Parity lines will not show the correct value until the next
bus cycle, thus the parity lines are unusable.

Question: In Page Mode operation, will RAS* be deasserted if the next
bank hit is an SRAM bank?
Answer: No.  RAS* for that bank will only be deasserted when there is
a miss on that particular DRAM bank or a processor Exception occurs.

Question: What do the WE* lines do if the user programs the Memory
Controller to external DSACK*?
Answer:  The WE* lines will be set to the system bus width, not
memory width.

Question: Are the DSACK signals generated by the memory controller shown
on the DSACK* pins?
Answer: Yes, except for fast termination cycles and internal bus cycles
(even when Show Cycles is enabled)

Question: If the memory controller is set up for a DRAM bank with
external DSACK, will the CAS Address be valid until DSACK* is externally
generated?
Answer: Yes

Question: What is the timing of the SIZ lines?
Answer: The SIZ lines follow the same timing as the FC lines and the
address lines (spec 150).

------------------------------------------------------------------------

4. IDMA Channels

Question: Will the assertion of DONE on an IDMA in buffer chaining mode
cause the IDMA to end the operation on the current buffer and chain to
the next available buffer, or will this cause the termination of the
chain?
Answer: It will cause termination of the chain. The current BD will be
closed, the Start bit in the CMR will be cleared, and the Reset bit
will be set. The User's Manual is incorrect.

------------------------------------------------------------------------
5. SDMA Channels

Question: Will the swapper correctly make a long word into Intel format?
Answer: Yes.  It will correctly swap words and long words.  It will not
properly swap long words in 16-bit bus mode however.
------------------------------------------------------------------------
6. Timers

Question:  I am using the PIT timer and am seeing the interval divided
by 128.  Why is this happening?
Answer:  This is coverend in the current UM Errata under SPCLK.  The PIT
is timed from SPCLK which is clocked at EXTAL/128 when the EXTAL input
is greater than 10 Mhz (i.e. MODCK1-0 = 01)

------------------------------------------------------------------------
7. Risc CP

Question:  If we use a ram microcode, how much space does that leave in
the internal DPRAM for BD's, etc...
Answer:  If a "small" (512 byte) microcode is used, then you will have
from DPRBASE+$200 to DPRBASE+$5FF (1024 bytes) for BDs.  If a "large"
(1024 byte) microcode is used, then you will have from DPRBASE+$400 to
DPRBASE+$5FF (512 bytes) for BDs. If you are not using all of the
facilities of the chip (i.e. not using an SCC, or an IDMA, or an
SMC, or the SPI) it is possible to get as many as 128 contiguous bytes
for BD space.

Question: How can I tell which version of the QUICC I am using?
Answer:  In order to determine the microcode revision number by checking
the "Rev_num" field detailed on page 7-6 of the QUICC UM.  The word
will be $0001 for Rev A silicon and $0002 for Rev B silicon.

------------------------------------------------------------------------
8. SCCs

------------------------------------------------------------------------
8a. Serial Interface

Question: Can I gate the clock into TCLK and RCLK
Answer: Yes.  This will allow you to either 1) Instantly turn off the
transmitter or 2) Selectively receive data.  On the receive side,
realize that the data will not move out of the FIFO into the Buffer
until you give it enough clocks to shift out.  The small or large FIFO
settings have no affect on the number of clocks before the data is
placed in the BD.

------------------------------------------------------------------------
8b. UART Controller

------------------------------------------------------------------------
8c. HDLC Controller

Question: Why am I not getting RXF interrupts after I receive an HDLC
frame?
Answer: Check the RFTHR setting in the HDLC memory map.  This word
determines how many frames will be received by the HDLC controller
before it sets the RFX bit in the event  register.  If RFTHR is
accidentally set to $0000, then 64K frames will be received before the
RXF interrupt will occur.

------------------------------------------------------------------------
8d. HDLC Bus Controller

Question: Can I use Manchester encoding to send the clock with the data?
Answer: No, the collision algorithm will fail unless standard NRZ is
used.

Question: How can I tell when the QUICC is retransmitting in HDLC
bus mode?
Answer: In HDLC bus mode, the QUICC hides details of collisions and
retransmissions from the user software and the user is not informed of
any collisions. Provided that collisions occur during transmission of the
first two buffers of a frame, the CP will handle each collision and
re-transmit the whole frame automatically. The user is not informed of
this even if the QUICC has to try retransmitting the frame many times.
There are no interrupts or event bits for collisions. The only way the
user software can observe collisions is by monitoring the RETRC counter.

------------------------------------------------------------------------
8e. Appletalk Controller
------------------------------------------------------------------------
8f. BISYNC Controller
------------------------------------------------------------------------
8g. Transparent Controller

Question:  I can't get the SCC to recognize the CD/CTS pins in external
sync mode.
Answer:  The CD/CTS pins behave as follows:
1) Internal Loopback mode - The pins are ignored.  The Transmitter and
Receiver are instantly synced.
2) Sync mode is pulse - The sync signals are edge sensitive ...
3) Sync mode is envelope - only the receiver is edge sensitive. The
reason:
CTS can be active low all the time or used as a I/O (RTS is the envelope
of the frame).
CD should be edge sensitive in order not to synchronize in the middle of
a frame
(for example after reset).

Question: Is there any way to get the Transparent Controller to ignore
synchronization all together?
Answer: Yes. The best thing to do is to tie a parallel I/O pin to the CTS
and CD lines.  Then after you enable the receiver and transmitter,
provide a falling edge by manipulating the I/O pin in software.
Another possibility is to enable the receiver and transmitter for the
SCC in loopback mode and then change the GSMR diag mode bits to 00
while enabled.

------------------------------------------------------------------------
8h. Ethernet Controller

Question: Which SCC do I use to run Ethernet?
Answer: You can use any SCC for Ethernet.  It is suggested that you
use SCC1 due to its larger FIFO.

Question: Can I run more than one Ethernet Channel?
Answer: Yes, the QUICC is capable of running two 10 MBps Ethernet
Channels.  In that case, the second channel should be SCC2 but may
be any of the other SCCs.

Question: Can I run full-duplex Ethernet?
Answer: Yes, you can use 1 SCC for Transmit and another SCC for Receive.
Connect the SIA RxD, RCLK and RENA signals to one SCC, and TxD, TCLK and
TENA to the other SCC. CLSN should not be used. This assumes that your
transceiver can handle full-duplex Ethernet. In Rev B of the part, you
will be able to use 1 SCC for both Transmit and Receive.

Question: How can I tell an "EN" part from a non "EN" part?
Answer:  One way to detemine if the part is a EN360 is to set the SCC
to Ethernet mode and set TEN=0. Then read the RTS_ (TENA) pin.  If it
is zero, it is a EN360 part, if not it's a plain 360.

Question: I have a QUADS board and I can't seem to get the demo code
for Ethernet to work.
Answer: Be sure to use the "ESLAVE.ASM" code and not the "ETHN_EX1.ASM"
code.  Read the note at the top of the "ESLAVE.ASM" code.

Question: When I use the QUADS board in Ethernet mode, the LEDs don't
light up.
Answer: The LEDs on the board are connected to the EEST (which may or may
not be on your board) and thus may not light up even though the interface
is working.

------------------------------------------------------------------------

9. SMCs

Question:  I am having problems running UART mode on the SMCs.
Answer:  There are currently many problems with SMCs running UART.
Check the device errata (rev A.2) for more information.


9a. UART Mode
------------------------------------------------------------------------
9b. Transparent Mode
------------------------------------------------------------------------
10. SPI
------------------------------------------------------------------------
11. Parallel Ports

Question:  In the manual, it states that PADIR should be set to 0
(input) and PAPAR should be set to 1 in order to get the signals RXD1
and TXD1 out.  Shouldn't PADIR be set to 1 (output) for bit 1 to get
TXD1 out?
Answer: No.  PADIR only means direction when the pin is set up to be a
general purpose I/O pin.  Follow the tables on pages 7-351, 7-356, and
7-358 for instructions on how to set up the pins to be a certain signal.

Question: What is the transfer rate for the PIP?
Answer: The preliminary transfer rate for the PIP is 625 Kb/sec,
assuming 8-bit transfers at 25 MHz.

------------------------------------------------------------------------
12. 040 Companion Mode/Slave Mode

Question:  I would like to use a QUICC and an 040.  I am worried about
excessive clock skew between the 040 and QUICC clock inputs.
Answer:  If you feed a 25 MHz clock in to QUICC and then use the output
of CLKO2 as a 50 MHz input to the 040, we guarantee that it will meet
the spec. Thus PCLK should be connected to CLK02 and BLCK should be
connected to XTAL

Question: Does the DRAM controller support interleaved memory in 040
companion mode to allow 2-1-1 bursts.
Answer: No. You would have to build your own memory controller for those
banks that you wish to interleave.

Question: Can the memory controller use Page Mode in 040 companion mode.
Answer: No.  Any memory bank that can be accessed by the 040 cannot use
page mode.

Question: In the A.2 Device Errata, it says to enter slave mode, the
config pins should be set to master mode until "a few clocks" after
the PLL locks.  How many clocks is "a few"?
Answer: 10 clocks is a good number to use.

------------------------------------------------------------------------

13. Electrical Specs

Question: What is the derating factor for the QUICC pins?
Answer: At this time we do not have that information.

Question: Are the theta-JA and theta-JC ratings available yet?
Answer:Thermal Resistance-Junction to case
PQFP theta-JC 9.7 oC/W
PGA  theta-JC 3   oC/W
Thermal Resistance-Junction to Ambient
PQFP theta-JA 35.8 oC/W
PGA  theta-JA 22.8 oC/W

Question: Do we have updated power specs?
Answer:
Char.    Symbol     Sys.Clk.Frq.  BRGCLK  SyncCLK  Typ   Max  Unit
Normal1   PD          25 MHz       25 Mhz  25 MHz  300   (***)  mA
Normal2   PD          25 MHz       25 Mhz  25 MHz  250   -    mA
Normal3   PD          25 MHz       25 Mhz  25 MHz  180   -    mA
Normal1 = All blocks on chip working at full frequency and power.
Normal2 = Same as Normal1, but CPU32+ is disabled.
Normal3 = Same as Normal1, but CPU32+ and both IDMAs are disabled.
Normal2 and Normal3 do not have Max values, because these situations
are not tested for each device, but are included for reference
purposes only.
(***)  This value will be finalized soon.  For now, use 450mA until
we know for sure.


------------------------------------------------------------------------
14. Packaging Specs

Question: Who manufactures sockets for the QUICC?
Answer: For PGA sockets, contact AMP.
    For PGA to QFP adapters, contact:
    Emulation Technology - [phone]
    ISI - [phone]

------------------------------------------------------------------------
15. Current Device Availability
a. Parts/QUADS board availability

We are currently sampling both backages of the 68360 and QUADS board.
For specific information on part availability and lead times, call your
local Motorola sales office.

------------------------------------------------------------------------
16. QUADS Board

Question: I would like to design a board which will interface to the
QUADS board.  What are the dimensions of the board?
Answer: The QUADS board is the same width as a VMEBus card and the
connectors are in the same position (though are the reverse gender).
For specific dimensions, contact the Data Communications Group.

Question: What are the manufacturer names and part numbers for the
connectors on the QUADS board?
Answer:
P1 and P2 - Manufactured by ELCO part number 26 8477 096 002 025
            these are DIN 96 pin right angled female connectors
The opposite DIN 96 pin right angled male connectors are:
1. Wire-wrap connector, ELCO part number 16 8457 096 004 025
   2 connectors are supplied with each QUADS.
2. PC board connector, ELCO part number 16 8457 096 002 025

ELCO Corporation
Huntingdon Industrial Park
Huntingdon, PA 16652
Phone [phone]

P11 - 5v power connector. The 3 terminal socket is manufactured
      by Wieland Bamberg part number 8113S 253303353
The required 3 terminal plug is Wieland Bamberg
part number 8113B 253200353

P12 - 12v power connector. The 2 terminal socket is manufactured
      by Wieland Bamberg part number 8113S 253303253
The required 2 terminal plug is Wieland Bamberg
part number 8113B 253200253

Wieland Industrie
D-8600  Bamberg Brennerstrasse 10-14
Germany
FAX - (09 51) 404-198


Question: What Chip Selects and Interrupt pins are available on the
QUADS board?
Answer: Chip Selects 1-6 are available from the master from P2.  IRQ
lines 1-7 are available on P2.  If you wish to have external interrupts,
you will have to make sure that the slave is not going to generate that
level of interrupt.

------------------------------------------------------------------------
16a. QUICCBug

------------------------------------------------------------------------
16b. 360sw

Question: When I attempt to run "360sw", it doesn't run.  I just get an
error.
Answer: Two things may be happening.  1) Try it again.  360sw doesn't
work the first time you run it after a power-on reset.  It will work
after that.  2) Do an MD b0000;di.  If the code is garbage, it means
that you have not programmed your flash.  Follow the directions in the
first_start.txt document that you received on disk with your QUADS
board.

------------------------------------------------------------------------
16c. Documentation

------------------------------------------------------------------------

17. Demo Code

The Following Code exists of the Motorola BBS BBS [phone]

registrn.txt     1895 Aug 20 93 To insure you are notified of updates
                                to the software, please fill out and
                                send in this form
readv0_3.txt     3608 Aug 20 93 Readme file for the v0.3 QUADS
                                Software Release
bsynv0_3.zip    12141 Aug 20 93 Directory with Bisync C source files
docv0_3.zip      4994 Aug 20 93 Drivers documentation directory
drvsv0_3.zip   176024 Aug 20 93 68360 Chip Driver C Source Directory
exsv0_3.zip     17224 Aug 20 93 Directory with example ".g"
                                configuration files for the 68360
ibmv0_3.zip    279099 Aug 20 93 Directory with Host Software to run
                                with an IBM-PC
incv0_3.zip     13027 Aug 20 93 Include files for the Drivers
init_exs.zip    27204 Aug 20 93 Directory with sample code that sets
                                up the serial channel for either UART,
                                HDLC,or Ethernet mode

                                These correspond to the examples
                                in the MC68360 User's Manual.
libv0_3.zip     24020 Aug 20 93 Libraries C source for the 68360
                                Drivers
lapbv1_0.zip     9968 Aug 20 93 LAPB .h files only
lapdv1_0.zip    10058 Aug 20 93 LAPD .h files only
modsv0_3.zip   687592 Aug 20 93 Directory with S record listing for
                                the QUADS Software User Interface
                                Software (360sw, Object code for
                                the Driver, LAPB, LAPD, and X.25).
                                Also contained in the directory is
                                the S record listing for the
                                CPU32bug Debug Monitor (QUICCbug)
                                for the boot EPROM.
psndv0_3.zip    22199 Aug 20 93 (Optional) C source code for the
                                object code download
quads_rn.txt     2801 Aug 20 93 QUADS Software Release Notes for
                                Version 3.0
srcv0_3.zip     28061 Aug 20 93 Source code examples for interfacing
                                with chip drivers and other modules
sunv0_3.zip     89325 Aug 20 93 Directory with Host Software to
                                run with a SUN/4
x25v1_0.zip     18611 Aug 20 93 X.25 .h files only

tdrive.zip       5320 Oct 20 93 This code has been written to illustrate
                                the "Taking a QUICC Test Drive"
                                section of the 68360 User's Manual
                                pages 9-13 through 9-16 (steps 1-14).
                                It demonstrates the initialization
                                of both a master and slave QUICC and
                                could be used as the framework for a
                                BOOT PROM which could be placed
                                in a target system.

pit.zip          1288 Oct 21 93 This code is an example of how to use
                                the PIT timer to perform a periodic
                                event.  This particular code toggles
                                PB0 to create a square wave every
                                420us on a 25 MHz QUICC.

uart.zip         4441 Oct 25 93 This file illustrates the transmission
                                and reception of UART data utilizing
                                4 BDs and an interrupt-driven receive
                                routine.

------------------------------------------------------------------------

18. Application Notes

The following is a list of all current application notes not included in
the manual.

Booting an MC68360/68EC040 from a Single 8 bit Eprom - 7/1/93
Multiple QUICC Design Concept - 9/28/93

------------------------------------------------------------------------
19. New Questions

Question: How can I tell an "EN" part from a non "EN" part? Answer:  One
way to detemine if the part is a EN360 is to set the SCC to Ethernet mode
and set TEN=0. Then read the RTS_ (TENA) pin.  If it is zero, it is a
EN360 part, if not it's a plain 360.

Question: What are the manufacturer names and part numbers for the
connectors on the QUADS board?
Answer:
P1 and P2 - Manufactured by ELCO part number 26 8477 096 002 025
            these are DIN 96 pin right angled female connectors
The opposite DIN 96 pin right angled male connectors are:
1. Wire-wrap connector, ELCO part number 16 8457 096 004 025
   2 connectors are supplied with each QUADS.
2. PC board connector, ELCO part number 16 8457 096 002 025
ELCO Corporation
Huntingdon Industrial Park
Huntingdon, PA 16652
Phone [phone]
P11 - 5v power connector. The 3 terminal socket is manufactured
      by Wieland Bamberg part number 8113S 253303353
The required 3 terminal plug is Wieland Bamberg
part number 8113B 253200353
P12 - 12v power connector. The 2 terminal socket is manufactured
      by Wieland Bamberg part number 8113S 253303253
The required 2 terminal plug is Wieland Bamberg
part number 8113B 253200253
Wieland Industrie
D-8600  Bamberg Brennerstrasse 10-14
Germany
FAX - (09 51) 404-198

Question: Are the theta-JA and theta-JC ratings available yet?
Answer:Thermal Resistance-Junction to case
PQFP theta-JC 9.7 oC/W
PGA  theta-JC 3   oC/W
Thermal Resistance-Junction to Ambient
PQFP theta-JA 35.8 oC/W
PGA  theta-JA 22.8 oC/W

Question: How can I tell which version of the QUICC I am using?
Answer:  In order to determine the microcode revision number by checking
the "Rev_num" field detailed on page 7-6 of the QUICC UM.  The word
will be $0001 for Rev A silicon and $0002 for Rev B silicon.

Question:  I am using the PIT timer and am seeing the interval divided
by 128.  Why is this happening?
Answer:  This is coverend in the current UM Errata under SPCLK.  The PIT
is timed from SPCLK which is clocked at EXTAL/128 when the EXTAL input
is greater than 10 Mhz (i.e. MODCK1-0 = 01)

Question: I have a QUADS board and I can't seem to get the demo code
for Ethernet to work.
Answer: Be sure to use the "ESLAVE.ASM" code and not the "ETHN_EX1.ASM"
code.  Read the note at the top of the "ESLAVE.ASM" code.

Question: When I use the QUADS board in Ethernet mode, the LEDs don't
light up.
Answer: The LEDs on the board are connected to the EEST (which may or may
not be on your board) and thus may not light up even though the interface
is working.

Question: In the A.2 Device Errata, it says to enter slave mode, the
config pins should be set to master mode until "a few clocks" after
the PLL locks.  How many clocks is "a few"?
Answer: 10 clocks is a good number to use.

Question: What is the timing of the SIZ lines?
Answer: The SIZ lines follow the same timing as the FC lines and the
address lines (spec 150).

Question: Do we have updated power specs?
Answer:
Char.    Symbol     Sys.Clk.Frq.  BRGCLK  SyncCLK  Typ   Max  Unit
Normal1   PD          25 MHz       25 Mhz  25 MHz  300   (***)  mA
Normal2   PD          25 MHz       25 Mhz  25 MHz  250   -    mA
Normal3   PD          25 MHz       25 Mhz  25 MHz  180   -    mA
Normal1 = All blocks on chip working at full frequency and power.
Normal2 = Same as Normal1, but CPU32+ is disabled.
Normal3 = Same as Normal1, but CPU32+ and both IDMAs are disabled.
Normal2 and Normal3 do not have Max values, because these situations
are not tested for each device, but are included for reference
purposes only.
(***)  This value will be finalized soon.  For now, use 450mA until
we know for sure.

Question: What is the transfer rate for the PIP?
Answer: The preliminary transfer rate for the PIP is 625 Kb/sec,
assuming 8-bit transfers at 25 MHz.

Question: How can I tell when the QUICC is retransmitting in HDLC
bus mode?
Answer: In HDLC bus mode, the QUICC hides details of collisions and
retransmissions from the user software and the user is not informed of
any collisions. Provided that collisions occur during transmission of the
first two buffers of a frame, the CP will handle each collision and
re-transmit the whole frame automatically. The user is not informed of
this even if the QUICC has to try retransmitting the frame many times.
There are no interrupts or event bits for collisions. The only way the
user software can observe collisions is by monitoring the RETRC counter.

Question: Is it possible to run the QUICC from a 10 MHz external
oscillator and clock the CPU at 25 MHz?
Answer: Yes.  The system should be brought up with the MODCK pins
set to 01.  Once the system is running, the 128 prescaler should be
enabled and the MF set to 320.  (This is all done in the PLLCR)

Question: Is DPRAM cleared on hard reset?
Answer: No.

---
New/Changed Demo Code

init_exs.zip    Changed to fix error in the equate files for SCC4
        This did not affect the object code.
init_ex2.zip    A demonstration of an interrupt driven receive routine
        for UART, Transparent, and HDLC.  Also shows use of
        the UART Control Character Table, external syncing
        of Transparent Mode, and address recognition in HDLC.
uart.zip    removed. Now included in "init_ex2.zip"